1. Field of the Invention
The present invention relates to memory systems for computers, and more particularly to the design of a memory system that provides variable memory latency for read and/or write accesses to a synchronously accessed memory.
2. Related Art
New memory system designs have been developed to keep pace with rapid increases in processor clock speeds. As processors get faster, memory systems are under increasing pressure to provide data at faster rates to keep up with the processors. This has recently led to the development of new memory system designs. Latencies for memory accesses have been dramatically decreased by using page mode and extended data out (EDO) memory designs, which achieve a high burst rate and low latencies within a single page of memory. Another recent innovation is to incorporate a synchronous clocked interface into a memory chip, thereby allowing data from within the same page of memory to be clocked out of the memory in a continuous stream using the processor clock. Such memory chips, with clocked interfaces are known as synchronous random access memories.
Recently, standards such as Rambus and SyncLink have been developed to govern the transfer of data between memory and processor using such clocked interfaces. SyncLink, which will be known as IEEE Standard 1596.7, specifies an architecture that supports a 64M-bit memory with a data transfer rate of 1.6 gigabytes per second. SyncLink packetizes and pipelines the address, commands, and timing, and adds features that significantly increase the data bus speed, thereby providing fast memory access without losing the ability to move quickly from row to row or to obtain bursts of data. In the IEEE standard, a 10-bit upper bus is used for command and address transmission, and an 18-bit lower bus is used for data signals.
As processor clock speeds continue to increase, it is becoming increasing harder for memories with clocked interfaces to keep pace with processor clock speeds. More than one clock cycle of time may be required to read from or write to a synchronous memory. Furthermore, the amount of time required access a memory may depend upon the latency of a particular memory chip, and this latency can vary as different memory chips are included in a memory system. This makes it hard to design a memory architecture that can flexibly accommodate different memory chips.
What is needed is a memory system including a synchronous interface between processor and memory that provides more than one clock cycle of time for read and/or write accesses to the memory.
Additionally, what is needed is a memory system that provides a configurable latency for read and write accesses to a synchronously accessed memory in order to allow the memory system to operate with different memory devices and/or different processor clock speeds.